In recent years, the development of semiconductor devices which use an oxide semiconductor for a channel in place of amorphous silicon, low temperature polysilicon and single crystal silicon has been proceeding (for example, Japanese Laid Open Patent Publication No. 2016-139819). A semiconductor device which uses an oxide semiconductor as a channel can be formed with a simple structure and at a low temperature process similar to a semiconductor device which uses amorphous silicon as a channel. It is known that a semiconductor device which uses an oxide semiconductor as a channel has higher mobility than a semiconductor device which uses amorphous silicon as a channel. It is known that a semiconductor device which uses an oxide semiconductor as a channel has a low off-current.
In the top-gate type oxide semiconductor transistor disclosed in Japanese Laid Open Patent Publication No. 2016-139819, it is a problem to achieve both a reduction of the resistance of a source/drain region and an increase of the resistance of the channel region. In oxide semiconductors, carriers are generated due to oxygen defects, thereby the resistance value of the oxide semiconductor is reduced. That is, in the channel region, a treatment (oxidation treatment for example) for compensating for the oxygen defects is necessary, and in the source/drain region, a treatment (reduction treatment for example) for generating oxygen defects is necessary. For example, Japanese Laid Open Patent Publication No. 2016-139819 discloses a method of reducing the resistance of an oxide semiconductor layer in a source/drain region by a reduction treatment after the oxide semiconductor layer as a whole has been provided with high resistance using an oxidation treatment.
As is disclosed in Japanese Laid Open Patent Publication No. 2016-139819, in order to reduce the resistance of the source/drain region selectively in a top-gate oxide semiconductor transistor, it was necessary to perform special low resistance treatments such as a reduction treatment.